A semiconductor wafer for use in fabricating a semiconductor device is produced through the steps of, for example, chamfering, flattening, etching, mirror edge polishing, polishing, etc., which are performed after slicing a silicon single crystal ingot grown by the Czochralski method in the shape of a wafer. The semiconductor wafer thus produced is strictly controlled in terms of shape, and in recent years, there has been additional demand to improve dimensional precision of the chamfered shape.
One reason for this is, for example, due to the following situations. Increasingly employed for advanced devices using a large-diameter single crystal silicon wafer of 300 mm diameter or more is an immersion stepper based on a technique (immersion exposure technique) in which resolutions are enhanced by providing liquid (normally, pure water) between an objective lens and the silicon wafer, but in the case of exposure using such a technique, if there are variations in shape among chamfered portions of the wafer, the liquid is readily caused to leak from the chamfered portions of the wafer when scanning the outermost portion of the wafer. Therefore, there has been increasing demand on chamfered geometry of the wafer, concerning reviews, such as reduction in chamfer width, and improvements in dimensional precision.
In addition, time periods for temperature rise/fall during the heating cycle tend to be reduced in order to enhance productivity in the heat treatment process for diffusion and film formation during the device process. In this case, there is a concern that the silicon wafer might receive greater thermal shock than conventionally with the result that the wafer cracks. At the same time, the speed of feeding or suchlike is increased, and therefore there is a concern that the wafer might crack due to contacting the chamfered portions of the wafer with a feeder or a wafer carrier. In order to render the silicon wafer unsusceptible to their heat stress and mechanical stress, the necessity has arisen to strictly define the chamfered shape dimensions of the silicon wafer.
As for the standard for the chamfered shape of the silicon wafer, device makers, which are customers, often present the chamfered shapes of product silicon wafers they need. As shown in FIG. 5, board makers design, in drawings, intended chamfer values (process control values) for wafers subjected to a chamfering process, i.e., wafers sliced from an ingot (as-sliced wafers), flattened wafers, etched wafers, ground wafers, etc., based on process values for wafer thickness designed process by process, and process control is performed based on the intended chamfer values. Processing widths are typically 50 to 100 μm for the flattening process, 10 to 40 μm for the etching process, and 10 to 20 μm for the polishing process. Note that “flattening” as referred to hereinbelow encompasses various flattening methods, such as lapping and surface grinding.
As shown in FIG. 6, dimensions are defined for the standard for the chamfered shape. Roughly defined are: X1 for a chamfer width on the front surface side of the wafer; X2 for a chamfer width on the back surface side of the wafer; θ1 for an angle between the front surface of the wafer and the front surface side bevel; θ2 for an angle between the back surface of the wafer and the back surface side bevel; X3 for a distance between intersections of lines extended from the front and back surface side bevels of the wafer and a vertical line along an end surface; and R1 and R2 respectively for radii of round portions which are generally arced portions of the front and back surfaces of the wafer.
A grindstone for chamfering is produced based on the standard for the chamfered shape as predefined above, and the chamfering process is performed using the grindstone for chamfering, but in some cases, when a product wafer subjected to flattening, etching, polishing, etc., after actual chamfering is measured for dimensions of its chamfered portions, the dimensions might greatly deviate from target dimensions of the chamfered portions. In addition, such a phenomenon tends to be noticeable particularly for wafers with the lengths X1 and X2 reduced as frequently requested by customers these days.
To address the above problem, the following measures have been taken conventionally.
As shown in FIG. 3, in the conventional method, first, (a) a drawing indicating a target chamfered shape is provided by a customer, and (b) a grindstone for chamfering is designed and produced to achieve the chamfered shape. Next, (c) an as-sliced wafer serving as a dummy wafer is prepared, and (d) chamfered, and thereafter (e) the dummy wafer is measured for its chamfered shape. Next, (f) the dummy wafer is introduced into post-chamfering processes, (g) the wafer having undergone the final stage is measured for its chamfered shape to (h) obtain a difference from the target chamfered shape, and if there is a significant deviation, (i) a groove geometry is designed again to produce a grindstone for chamfering. Then, an as-sliced wafer serving as a dummy wafer is prepared to perform steps (c) to (h) again, and if the difference between the chamfered shape measured in step (g) and the target chamfered shape is sufficiently small, the dimension values measured in step (e) are set as intended chamfer values for the wafer to be produced, i.e., intended control values for the process of chamfering the product wafer, before (j) advancing to the product process for production of the product wafer.
Going through such steps is extremely inefficient because reproduction of the grindstone for chamfering takes one month or more, for example.
Recently, there is also performed a method as shown in FIG. 4 in which steps (a) to (h) are performed in the same manner as in the conventional method shown in FIG. 3 to process a dummy wafer to the final stage and thereafter obtain a difference between the chamfered shape of the dummy wafer and a target chamfered shape, and (i) the groove geometry of a grindstone for chamfering is modified on a chamfering machine by means of a chamfered shape correcting function provided in the chamfering machine (Japanese Unexamined Patent Publication (Kokai) No. 2005-153085).
However, even in the case of going through such steps, the processing of the silicon wafer still needs to be performed to its final stage, and there was a disadvantage in that it normally took about three to seven days until a desired chamfered shape was obtained.